1. Field Of The Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for providing deterministic read access to main memory in a computer system utilizing multiple buses.
2. History of the Prior Art
Historically, personal computers have utilized a single bus to transfer data between different internal components of the system. In personal computers using central processing units (CPUs) designed and manufactured by Intel Corporation of Santa Clara, Calif., such buses have typically been designed as either an Industry Standard Association (ISA) bus or an Expanded Industry Standard Association (EISA) bus. The ISA bus is a sixteen bit data bus while the EISA bus is thirty-two bits wide. Both the ISA bus and the EISA bus typically operate at a frequency just over eight megahertz. These bus widths and the rates at which each of these buses is capable of operating have limited the speed at which a computer can operate so there have been a number of attempts to increase bus speed.
One recently implemented method of increasing bus speed is to provide an additional, so called, "local bus" which is more closely associated with the central processor than either of the above-mentioned buses and which is capable of running at speeds closer to the speeds at which the central processor itself runs. Those system components which require faster operation than has been available using the slower buses (such as an output display card for driving an output display device) are joined to this faster local bus. The slower ISA or EISA bus is continued in essentially unchanged form as a secondary bus, and those components which are able to tolerate longer access times are associated with the slower bus. Although the theory behind using a local bus appears reasonable, many local bus designs have actually slowed in some respects the operation of the computers with which they are implemented.
Intel Corporation has designed a local bus which may be associated in a computer system both with an Intel processor and with other buses such as an ISA bus or an EISA bus (each of which is hereinafter referred to broadly as a secondary bus). This local bus is able to transfer data more rapidly for selected components of the system without the conflicts and bottlenecks which arise using other local bus systems. This bus is referred to as the "peripheral component interconnect" (PCI) bus. The PCI bus is thirty-two bits wide and is capable of operating at frequencies up to thirty-three megahertz.
A computer system using the PCI bus includes, in addition to the physical PCI bus conductors, a first bridge circuit which controls the transfer of data among the PCI bus, CPU main memory; and a second bridge circuit which controls the transfer of data between the secondary bus and the PCI bus. These bridges are necessary in order to synchronize the transfer of data where buses are operating at different data transfer rates. Thus, the arrangement is such that components on the PCI bus utilize the first bridge in transfers of data involving the central processor or main memory and the second bridge in transfers of data involving components on the secondary bus. On the other hand, components on the secondary bus utilize the second bridge circuit, the PCI bus, and the first bridge in transfers of data involving the central processor or main memory; and utilize the second bridge in transfers of data involving the components on the PCI bus.
Modern computer systems use bus masters to speed the operation of the system. A bus master is a component capable of originating and controlling the transfer of data on a bus. Typically a bus master includes its own processor and operates on its own internal clock. Bus masters may be associated with either the PCI bus or the secondary bus in a computer system using a PCI bus. A peculiarity of the architecture utilized in implementing the PCI bus is that there are situations in which it might be impossible for a PCI bus master desiring to read data from main memory to ever gain access to main memory to complete the read operation. It is desirable to provide a method and apparatus for eliminating such a condition.